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1

3D nanowire gate-all-around transistors: Specific integration and electrical features

C. Dupré, T. Ernst, V. Maffini-Alvaro, V. Delaye, J.-M. Hartmann, S. Borel, C. Vizioz, O. Faynot, G. Ghibaudo, S. Deleonibus

Journal:

Solid-State Electronics

Année:

2008

Langue:

english

Fichier:

PDF, 795 KB

english, 2008

2

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

F. Lime, R. Ritzenthaler, M. Ricoma, F. Martinez, F. Pascal, E. Miranda, O. Faynot, B. Iñiguez

Journal:

Solid-State Electronics

Année:

2011

Langue:

english

Fichier:

PDF, 582 KB

english, 2011

3

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Khandelwal, S., Chauhan, Y. S., Lu, D. D., Venugopalan, S., Ahosan Ul Karim, M., Sachid, A. B., Nguyen, B.-Y., Rozeau, O., Faynot, O., Niknejad, A. M., Hu, C. C.

Journal:

IEEE Transactions on Electron Devices

Année:

2012

Langue:

english

Fichier:

PDF, 845 KB

english, 2012

4

Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

Fernandez, Cristina, Rodriguez, Noel, Ohata, Akiko, Gamiz, Francisco, Andrieu, Francois, Fenouillet-Beranger, Claire, Faynot, Olivier, Cristoloveanu, Sorin

Journal:

IEEE Electron Device Letters

Année:

2013

Langue:

english

Fichier:

PDF, 429 KB

english, 2013

5

Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

Koyama, M., Cassé, M., Barraud, S., Ghibaudo, G., Iwai, H., Faynot, O., Reimbold, G.

Journal:

Solid-State Electronics

Année:

2015

Langue:

english

Fichier:

PDF, 929 KB

english, 2015

6

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model

Pelloux-Prayer, J., Cassé, M., Triozon, F., Barraud, S., Niquet, Y.-M., Rouvière, J.-L., Faynot, O., Reimbold, G.

Journal:

Solid-State Electronics

Année:

2016

Langue:

english

Fichier:

PDF, 2.07 MB

english, 2016

7

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Paz, Bruna Cardoso, Cassé, Mikaël, Barraud, Sylvain, Reimbold, Gilles, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

Journal:

Solid-State Electronics

Année:

2017

Langue:

english

Fichier:

PDF, 1.29 MB

english, 2017

8

Agglomeration control during the selective epitaxial growth of Si raised sources and drains on ultra-thin silicon-on-insulator substrates

C. Jahan, O. Faynot, L. Tosti, J.M. Hartmann

Journal:

Journal of Crystal Growth

Année:

2005

Langue:

english

Fichier:

PDF, 543 KB

english, 2005

9

Performance and physics of sub-50 nm strained Si on Si1−xGex-on-insulator (SGOI) nMOSFETs

F. Andrieu, T. Ernst, O. Faynot, O. Rozeau, Y. Bogumilowicz, J.-M. Hartmann, L. Brévard, A. Toffoli, D. Lafond, B. Ghyselen, F. Fournel, G. Ghibaudo, S. Deleonibus

Journal:

Solid-State Electronics

Année:

2006

Langue:

english

Fichier:

PDF, 847 KB

english, 2006

10

Electrical characteristics related to silicon film thickness in advanced FD SOI–MOSFETs

A. Ohata, M. Cassé, O. Faynot

Journal:

Solid-State Electronics

Année:

2008

Langue:

english

Fichier:

PDF, 581 KB

english, 2008

11

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

Gaillardin, Marc, Paillet, Philippe, Ferlet-Cavrois, Veronique, Baggio, Jacques, McMorrow, Dale, Faynot, Olivier, Jahan, Carine, Tosti, Lucie, Cristoloveanu, Sorin

Journal:

IEEE Transactions on Nuclear Science

Année:

2007

Langue:

english

Fichier:

PDF, 1.12 MB

english, 2007

12

Silicon-On-Diamond layer integration by wafer bonding technology

Rabarot, M., Widiez, J., Saada, S., Mazellier, J.-P., Lecouvey, C., Roussin, J.-C., Dechamp, J., Bergonzo, P., Andrieu, F., Faynot, O., Deleonibus, S., Clavelier, L., Roger, J.P.

Journal:

Diamond and Related Materials

Année:

2010

Langue:

english

Fichier:

PDF, 3.96 MB

english, 2010

13

Modeling of low frequency noise in FD SOI MOSFETs

El Husseini, J., Martinez, F., Valenza, M., Ritzenthaler, R., Lime, F., Iñiguez, B., Faynot, O., Le Royer, C., Andrieu, F.

Journal:

Solid-State Electronics

Année:

2013

Langue:

english

Fichier:

PDF, 701 KB

english, 2013

14

[IEEE 2011 Spanish Conference on Electron Devices (CDE) - Palma de Mallorca, Spain (2011.02.8-2011.02.11)] Proceedings of the 8th Spanish Conference on Electron Devices, CDE'2011 - A simple analytical and explicit compact model for the drain current of UTB SOI MOSFETs

Lime, F., Ritzenthaler, R., Iniguez, B., Miranda, E., Martinez, F., Pascal, F., Faynot, O.

Année:

2011

Langue:

english

Fichier:

PDF, 204 KB

english, 2011

15

Investigation of Quantum Effects in Ultra-Thin Body Single- and Double-Gate Devices Submitted to Heavy Ion Irradiation

Munteanu, D., Ferlet-Cavrois, V., Autran, J. L., Paillet, P., Baggio, J., Faynot, O., Jahan, C., Tosti, L.

Journal:

IEEE Transactions on Nuclear Science

Année:

2006

Langue:

english

Fichier:

PDF, 527 KB

english, 2006

16

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Reboh, S., Coquand, R., Barraud, S., Loubet, N., Bernier, N., Audoit, G., Rouviere, J.-L., Augendre, E., Li, J., Gaudiello, J., Gambacorti, N., Yamashita, T., Faynot, O.

Journal:

Applied Physics Letters

Année:

2018

Langue:

english

Fichier:

PDF, 2.18 MB

english, 2018

17

[IEEE 2019 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2019.12.7-2019.12.11)] 2019 IEEE International Electron Devices Meeting (IEDM) - Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transitors

Reboh, S., Boureau, V., Yamashita, T., Faynot, O., Coquand, R., Loubet, N., Bernier, N., Augendre, E., Chao, R., Li, J., Zhang, J., Muthinti, R.

Année:

2019

Fichier:

PDF, 12.62 MB

2019

18

New numerical low frequency noise model for front and buried oxide trap density characterization in FDSOI MOSFETs

J. El Husseini, F. Martinez, J. Armand, M. Bawedin, M. Valenza, R. Ritzenthaler, F. Lime, B. Iñiguez, O. Faynot, C. Le Royer

Journal:

Microelectronic Engineering

Année:

2011

Langue:

english

Fichier:

PDF, 493 KB

english, 2011

19

Analysis of SIMOX metal-oxide-semiconductor transistors operated in the high temperature range

T. Ouisse, G. Reichert, S. Cristoloveanu, O. Faynot, B. Giffard

Journal:

Materials Science and Engineering: B

Année:

1995

Langue:

english

Fichier:

PDF, 233 KB

english, 1995

20

Low-temperature electrical characterization of fully depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 gate stack for the 32-nm technology node

S. Feruglio, F. Andrieu, O. Faynot, G. Ghibaudo

Journal:

Année:

2009

Langue:

english

Fichier:

PDF, 733 KB

english, 2009

21

Multiple gate devices: advantages and challenges

T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, S. Deleonibus

Journal:

Microelectronic Engineering

Année:

2005

Langue:

english

Fichier:

PDF, 1.34 MB

english, 2005

22

Multigate silicon MOSFETs for 45 nm node and beyond

T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, B. Previtali, T. Ernst, S. Deleonibus

Journal:

Solid-State Electronics

Année:

2006

Langue:

english

Fichier:

PDF, 231 KB

english, 2006

23

A systematic investigation of work function in advanced metal gate–HfO2–SiO2 structures with bevel oxide

Atsushi Kuriyama, Jérôme Mitard, Olivier Faynot, Laurent Brévard, Laurence Clerc, Amélie Tozzo, Vincent Vidal, Simon Deleonibus, Hiroshi Iwai, Sorin Cristoloveanu

Journal:

Solid-State Electronics

Année:

2007

Langue:

english

Fichier:

PDF, 1012 KB

english, 2007

24

FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

C. Fenouillet-Beranger, S. Denorme, P. Perreau, C. Buj, O. Faynot, F. Andrieu, L. Tosti, S. Barnola, T. Salvetat, X. Garros, M. Cassé, F. Allain, N. Loubet, L. Pham-Nguyen, E. Deloffre, M. Gros-Jean,

Journal:

Solid-State Electronics

Année:

2009

Langue:

english

Fichier:

PDF, 789 KB

english, 2009

25

Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET)

C. Dupré, T. Ernst, E. Bernard, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Cristoloveanu, G. Ghibaudo, O. Faynot, S. Deleonibus

Journal:

Solid-State Electronics

Année:

2009

Langue:

english

Fichier:

PDF, 1.15 MB

english, 2009

26

Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides

T. Rudenko, V. Kilchytska, S. Burignat, J.-P. Raskin, F. Andrieu, O. Faynot, Y. Le Tiec, K. Landry, A. Nazarov, V.S. Lysenko, D. Flandre

Journal:

Solid-State Electronics

Année:

2010

Langue:

english

Fichier:

PDF, 915 KB

english, 2010

27

Compact analytical modeling of SOI partially depleted MOSFETs with LETISOI

O. Faynot, T. Poiroux, J.L. Pelloie

Journal:

Solid-State Electronics

Année:

2001

Langue:

english

Fichier:

PDF, 412 KB

english, 2001

28

0.25 μm fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters

M Vanmackelberg, C Raynaud, O Faynot, J.-L Pelloie, C Tabone, A Grouillet, F Martin, G Dambrine, L Picheta, E Mackowiak, P Llinares, J Sevenhans, E Compagne, G Fletcher, D Flandre, V Dessard, D Vanhoe

Journal:

Solid-State Electronics

Année:

2002

Langue:

english

Fichier:

PDF, 547 KB

english, 2002

29

Lateral coupling and immunity to substrate effect in ΩFET devices

R. Ritzenthaler, S. Cristoloveanu, O. Faynot, C. Jahan, A. Kuriyama, L. Brevard, S. Deleonibus

Journal:

Solid-State Electronics

Année:

2006

Langue:

english

Fichier:

PDF, 487 KB

english, 2006

30

In-depth electrical characterization of sub-45 nm fully depleted strained SOI MOSFETs with TiN/HfO2 gate stack

S. Feruglio, F. Andrieu, O. Faynot, G. Ghibaudo

Journal:

Solid-State Electronics

Année:

2008

Langue:

english

Fichier:

PDF, 1.85 MB

english, 2008

31

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

S. Burignat, D. Flandre, M.K. Md Arshad, V. Kilchytska, F. Andrieu, O. Faynot, J.-P. Raskin

Journal:

Solid-State Electronics

Année:

2010

Langue:

english

Fichier:

PDF, 981 KB

english, 2010

32

Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

T. Signamarcheix, F. Andrieu, B. Biasse, M. Cassé, A.-M. Papon, E. Nolot, B. Ghyselen, O. Faynot, L. Clavelier

Journal:

Solid-State Electronics

Année:

2011

Langue:

english

Fichier:

PDF, 667 KB

english, 2011

33

Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI)

S. Baudot, F. Andrieu, O. Faynot, J. Eymery

Journal:

Solid-State Electronics

Année:

2010

Langue:

english

Fichier:

PDF, 912 KB

english, 2010

34

3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Romain Ritzenthaler, François Lime, Olivier Faynot, Sorin Cristoloveanu, Benjamin Iñiguez

Journal:

Solid-State Electronics

Année:

2011

Langue:

english

Fichier:

PDF, 864 KB

english, 2011

35

Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit

V. Kilchytska, M.K. Md Arshad, S. Makovejev, S. Olsen, F. Andrieu, T. Poiroux, O. Faynot, J.-P. Raskin, D. Flandre

Journal:

Solid-State Electronics

Année:

2012

Langue:

english

Fichier:

PDF, 1003 KB

english, 2012

36

Analysis of the latch and breakdown phenomena in N and P channel thin film SOI MOSFET's as a function of temperature

Balestra, F., Jomaah, J., Ghibaudo, G., Faynot, O., Auberton-Herve, A.J., Giffard, B.

Journal:

IEEE Transactions on Electron Devices

Année:

1994

Langue:

english

Fichier:

PDF, 388 KB

english, 1994

37

A physically based relation between extracted threshold voltage and surface potential flat band voltage for MOSFET compact modeling

Benson, J., D'Halleweyn, N.V., Redman-White, W., Easson, C.A., Uren, M.J., Faynot, O., Pelloie, J.-L.

Journal:

IEEE Transactions on Electron Devices

Année:

2001

Langue:

english

Fichier:

PDF, 73 KB

english, 2001

38

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

Nuo Xu, Ho, B., Andrieu, F., Smith, L., Bich-Yen Nguyen, Weber, O., Poiroux, T., Faynot, O., Tsu-Jae King Liu

Journal:

IEEE Electron Device Letters

Année:

2012

Langue:

english

Fichier:

PDF, 538 KB

english, 2012

39

Multi- UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Noel, J.-P., Thomas, O., Jaud, M., Weber, O., Poiroux, T., Fenouillet-Beranger, C., Rivallin, P., Scheiblin, P., Andrieu, F., Vinet, M., Rozeau, O., Boeuf, F., Faynot, O., Amara, A.

Journal:

IEEE Transactions on Electron Devices

Année:

2011

Langue:

english

Fichier:

PDF, 1.25 MB

english, 2011

40

[IEEE 2010 IEEE International SOI Conference - San Diego, CA, USA (2010.10.11-2010.10.14)] 2010 IEEE International SOI Conference (SOI) - High performance and low variability fully-depleted strained-SOI MOSFETs

Mazurier, J., Weber, O., Andrieu, F., Allain, F., Tabone, C., Toffoli, A., Fenouillet-Beranger, C., Brevard, L., Tosti, L., Perreau, P., Belleville, M., Faynot, O.

Année:

2010

Langue:

english

Fichier:

PDF, 667 KB

english, 2010

41

[IEEE 2010 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2010.12.6-2010.12.8)] 2010 International Electron Devices Meeting - Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Faynot, O., Andrieu, F., Weber, O., Fenouillet-Beranger, C., Perreau, P., Mazurier, J., Benoist, T., Rozeau, O., Poiroux, T., Vinet, M., Grenouillet, L., Noel, J-P., Posseme, N., Barnola, S., Martin,

Année:

2010

Langue:

english

Fichier:

PDF, 655 KB

english, 2010

42

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Barraud, S., Berthome, M., Coquand, R., Casse, M., Ernst, T., Samson, M.-P., Perreau, P., Bourdelle, K. K., Faynot, O., Poiroux, T.

Journal:

IEEE Electron Device Letters

Année:

2012

Langue:

english

Fichier:

PDF, 484 KB

english, 2012

43

Deep-amorphization and solid-phase epitaxial regrowth processes for hybrid orientation technologies in SOI MOSFETs with thin body

A. Ohata, Y. Bae, S. Cristoloveanu, T. Signamarcheix, J. Widiez, B. Ghyselen, O. Faynot, L. Clavelier

Journal:

Microelectronics Reliability

Année:

2012

Langue:

english

Fichier:

PDF, 1.03 MB

english, 2012

44

[IEEE 2011 IEEE International SOI Conference - Tempe, AZ, USA (2011.10.3-2011.10.6)] IEEE 2011 International SOI Conference - An exercise of ET/UTBB SOI CMOS modeling and simulation with BSIM-IMG

Chen, Qiang, Zhong, Xinghua, Wu, Yanjun, Zhu, Nengyong, Huang, Wei, Lu, Darsen, Hu, Chenming, Nguyen, Bich-Yen, Faynot, Olivier

Année:

2011

Langue:

english

Fichier:

PDF, 435 KB

english, 2011

45

Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor

Deshpande, V., Barraud, S., Jehl, X., Wacquez, R., Vinet, M., Coquand, R., Roche, B., Voisin, B., Triozon, F., Vizioz, C., Tosti, L., Previtali, B., Perreau, P., Poiroux, T., Sanquer, M., Faynot, O.

Journal:

Solid-State Electronics

Année:

2013

Langue:

english

Fichier:

PDF, 2.31 MB

english, 2013

46

Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

Mazellier, Jean-Paul, Faynot, Olivier, Cristoloveanu, Sorin, Deleonibus, Simon, Bergonzo, Philippe

Journal:

Diamond and Related Materials

Année:

2008

Langue:

english

Fichier:

PDF, 359 KB

english, 2008

47

Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution

Nguyen, P., Andrieu, F., Cassé, M., Tabone, C., Perreau, P., Lafond, D., Dansas, H., Tosti, L., Veytizou, C., Landru, D., Kononchuk, O., Guiot, E., Nguyen, B.-Y., Faynot, O., Poiroux, T.

Journal:

Solid-State Electronics

Année:

2013

Langue:

english

Fichier:

PDF, 1.24 MB

english, 2013

48

Extreme insulating ultrathin diamond films for SOD applications: From coalescence modelling to synthesis

Lions, M., Saada, S., Bazin, B., Pinault, M.-A., Jomard, F., Andrieu, F., Faynot, O., Bergonzo, P.

Journal:

Diamond and Related Materials

Année:

2010

Langue:

english

Fichier:

PDF, 466 KB

english, 2010

49

[IEEE 2007 IEEE International Electron Devices Meeting - Washington, DC, USA (2007.12.10-2007.12.12)] 2007 IEEE International Electron Devices Meeting - Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

Barral, V., Poiroux, T., Andrieu, F., Buj-Dufournet, C., Faynot, O., Ernst, T., Brevard, L., Fenouillet-Beranger, C., Lafond, D., Hartmann, J.M., Vidal, V., Allain, F., Daval, N., Cayrefourcq, I., Tos

Année:

2007

Langue:

english

Fichier:

PDF, 4.44 MB

english, 2007

50

[IEEE 1999 IEEE International SOI Conference. Proceedings - Rohnert Park, CA, USA (4-7 Oct. 1999)] 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) - High frequency characterization of SOI dynamic threshold voltage MOS (DTMOS) transistors

Ferlet-Cavrois, V., Bracale, A., Fel, N., Musseau, O., Raynaud, C., Faynot, O., Pelloie, J.L.

Année:

1999

Langue:

english

Fichier:

PDF, 142 KB

english, 1999